Re: [myhdl-list] Bug in MyHDL compiler?

[David G. <dsg...@gm...>]

Hi Jan,
I'm trying to make register file that returns a read and write
function, the former which will be synthesized as a verilog function
and the latter as a task. I don't want to have to explicitly pass
around the register file's signals. Does that make sense?

Sent from my iPhone

On Sep 27, 2011, at 10:59 AM, Jan Decaluwe <ja...@ja...> wrote:

> On 09/27/2011 02:10 PM, David Greenberg wrote:
>> While considering other approaches for a register file, if I could
>> return functions that would be synthesized into tasks, then I could
>> have a very similar interface to the one I imagined.
>>
>> It seems that the hierarchy extractor could ignore these unknown
>> objects as long as they're used only during the elaboration phase.
>> Is there a technical reason this isn't done?
>
> I'm not very proud on the hierarchy extraction code, which I find
> tricky and confusing. I have tried to simplify it before, by
> imposing tougher restrictions on what it supports.
>
> The problem is that I use the general Python profiler. During
> profiling, all functions get traced. Currently, the only way
> I have to differentiate between general functions and those
> used to define MyHDL structure, is by looking at the return
> type.
>
> I assume that users will want this distinction, and therefore
> I consider anything that doesn't strictly comply with the
> definition of a MyHDL instance as something that doesn't
> participate in the structure.
>
> I don't understand exactly what you try to accomplish but
> there may be ways to do it today without changes. For
> example, you can play scoping games with top-level signals,
> and pass function as parameters etc. The convertor
> doesn't care, as long as it's in the elaboration phase.
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>     Python as a HDL: http://www.myhdl.org
>     VHDL development, the modern way: http://www.sigasi.com
>     World-class digital design: http://www.easics.com
>
>
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