Re: [myhdl-list] Cosimulation newbie questions

[Bob C. <Fl...@gm...>]

On 09/24/2011 07:50 PM, Christopher Felton wrote:
> Is there a particular issue you are having with co-simulation? Or does it seem like a steep learning curve? Which it might be if you have not used other HDL simulators. I think if you follow the examples and use Icarus that will get you pretty far.

I'm mainly trying to get a feel for how flexible my FPGA development process should be.  In software, we frequently create multiple independent tests for a single piece of code that runs in a single environment.  In hardware, it seems we should first do our basic testbenches in all available environments (myHDL, cosimulation, hardware).

In software we have many well-known metrics we use to determine when testing is thorough:  Static code inspection, modeling, input/output corner analysis, random vector analysis (black box testing), path/state analysis, coverage analysis, and the list goes on.  Embedded/real-time software basically gets tested to death.  We also need to test that our software responds appropriately in the presence of significant hardware failures.

Do equivalent metrics (and their support tools) exist in the hardware domain?  The test benches I've seen so far appear to primarily be simple I/O stimulus.  Do tools exist that ensure a testbench does indeed access all critical internal states (including corner cases)?  That all gates have been forced to change state at least once (coverage)?

Or do I need to insert instrumentation into my circuit to expose internal states for access by a more sophisticated testbench?  And couldn't some or all of the results acquired using such added instrumentation be invalidated when the circuit is run without the instrumentation?  I would imagine the synthesis output could be very different, resulting in some changed functionality in the implementation.

I suppose much of this may reside in the synthesis toolchain, something I have not yet thoroughly explored.  I don't yet understand some of the content of the WebPACK ISE synthesis reports.

For example, one concern for me would be finding the maximum usable clock rate for a particular design in a particular FPGA.  I haven't yet seen anything in a testbench that would help determine this.  In software, we are seldom worried if the CPU is going too fast!  Quite the opposite.

I'm wondering how gnarly I can expect my testing to get as my designs become more complex.

-BobC