Re: [myhdl-list] Cosimulation newbie questions

[Christopher F. <chr...@gm...>]

On 9/24/11 2:56 AM, Bob Cunningham wrote:
> I'm trying to get a better grasp of the limits of cosimulation within myHDL.  I've been reading this manual section (http://www.myhdl.org/doc/0.6/manual/cosimulation.html#only-passive-hdl-can-be-co-simulated) and I want to be very clear about the meaning of one phrase in that section: "time delays are meaningless in synthesizable code"
>
> Does this simply mean that, in a synthesized implementation, the delays are "whatever" they are, and nothing done in the cosimulation domain can properly account or even allow for them?  (I'm not yet a digital designer: I'm a 25-year veteran embedded/real-time software wonk and algorithm specialist finally making the leap into FPGAs.)
>

Couple ways to look at this, say you are co-simulating MyHDL and Verilog 
(not converted MyHDL -> Verilog).  And your Verilog code has the following:

   always(*) begin
       x = #10 y;
   end

The "delay" (#10) in Verilog (in the Verilog simulator) doesn't relate 
back to anything in the MyHDL world.  The Verilog simulator will have 
its time step based on the settings or `timescale and the MyHDL 
simulator has it time step, these may not be the same in other-words 
they Verilog simulator and MyHDL simulator simulation steps are not 
related.  They are syncronized when the MyHDL is the simulation master. 
  When the MyHDL testbench generates the singals that sync e.g. clocks.

A delay is not synthesizable, a synthesizer will not try and generate 
some circuit (wound wire) to match the delay.

In general, if you are converting MyHDL to Verilog/VHDL this should not 
be much of an issue, unless you have "yield delay(N)" in the code you 
are trying to convert (I don't know if that statement will convert, it 
might for the testbench conversions).

> As an aside, I've tried to run all the cosimulation examples and tests in the myHDL distribution (myhdl-0.7/cosimulation/* and myhdl-0.7/myhdl/test/conversion/*), but only Icarus works.  Where can I find more information about getting the other environments to work with myHDL cosimulation?  Or should I not worry about it, and simply stick with Iverilog?
>
> The main reason I want to use cosimulation is because WebPACK ISE is v-e-r-y s-l-o-w for even simple examples.  I want to invoke it only on designs that have a good chance of working the first time they are written to an FPGA.
>

I have successfully co-simulated with the following:

   iverilog (Icarus)
   vsim (Modelsim)
   cver (open-source cver)
   cvc  (Tachyon Design Automation)
   ncsim (Cadence)

I don't know if there is much reason not to use Icarus, unless there is 
some feature that it is missing and another simulator supports.  There 
might not be any directions explicitly on the wiki for other simulators. 
  If there is a different simulator you want to use, the newsgroup might 
be able to give some advice.

Regards,
Chris