[myhdl-list] Cosimulation newbie questions

[Bob C. <Fl...@gm...>]

I'm trying to get a better grasp of the limits of cosimulation within myHDL.  I've been reading this manual section (http://www.myhdl.org/doc/0.6/manual/cosimulation.html#only-passive-hdl-can-be-co-simulated) and I want to be very clear about the meaning of one phrase in that section: "time delays are meaningless in synthesizable code"

Does this simply mean that, in a synthesized implementation, the delays are "whatever" they are, and nothing done in the cosimulation domain can properly account or even allow for them?  (I'm not yet a digital designer: I'm a 25-year veteran embedded/real-time software wonk and algorithm specialist finally making the leap into FPGAs.)

As an aside, I've tried to run all the cosimulation examples and tests in the myHDL distribution (myhdl-0.7/cosimulation/* and myhdl-0.7/myhdl/test/conversion/*), but only Icarus works.  Where can I find more information about getting the other environments to work with myHDL cosimulation?  Or should I not worry about it, and simply stick with Iverilog?

The main reason I want to use cosimulation is because WebPACK ISE is v-e-r-y s-l-o-w for even simple examples.  I want to invoke it only on designs that have a good chance of working the first time they are written to an FPGA.

TIA,

-BobC