Re: [myhdl-list] From Python to Silicon: python-myhdl presentation

[Shakthi K. <sha...@gm...>]

Hi Christopher:

--- On Fri, Sep 16, 2011 at 11:35 PM, Christopher Felton
<chr...@gm...> wrote:
| This feeds an argument against the explicit logic walk through because,
| as you said, the focus is Python and Python-MyHDL, IMO.
\--

Yes, it is an exception. I found all the examples from the manual to
be simple and easy to follow except for the reasoning behind using the
XOR for the bin2gray example. Hence, the need for the explicit logic
walk.

---
| That is the point, a negative value assigned to an unsigned causes a
| value error (you won't see this in Verilog).  You need the correct
| bounds to represent a number.  Failing examples are as useful as correct
| examples.
\--

Makes sense! Will include them.

---
|  I was thinking a slide that summarizes
| up to the point (just before the pypy) will be a better transition to
| the pypy information.  Summarizing the design flow is one possibility.
\--

Will include this. Thanks for your feedback and prompt replies. Appreciate it!

SK

-- 
Shakthi Kannan
http://www.shakthimaan.com