Re: [myhdl-list] Driving constants

[Jan D. <ja...@ja...>]

On 09/06/2011 03:39 PM, Sébastien Bourdeauducq wrote:
> On 09/06/2011 03:39 PM, Jan Decaluwe wrote:
>>> The signals are created by the __init__ method of the parent class. I
>>> could of course add parameters to this __init__ method to define the
>>> initial value of the signals, but it's quite messy and inelegant.
>>
>> No, just use overloading, it works for constructors also.
>
> Well, yes, but it's still inelegant.

Not in my opinion. I would want to define a constant
at construction time, not through a driver. (In the
first case events at time 0 are avoided, in the second
case not necessarily.)

In my view, Verilog' assign for this purpose is a workaround
for the fact that Verilog didn't have initialization syntax
originally. (The reason why I don't use initialization
in conversion is because I fear some tools won't support
it.)

>> I infer that some signals may have constant values that are
>> different depending on the subclass.
>
> Yes.
>
> How about my proposition of yielding a special object "empty sensitivity
> list/constant driver" in the generators?

You can use 'yield None' today, but it's not supported by
conversion. Classes are neither, so perhaps you don't mind.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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