Re: [myhdl-list] Driving constants

[Sébastien B. <seb...@mi...>]

On 09/05/2011 12:49 AM, Jan Langer wrote:
> Maybe you got a reset signal and can use that to set the initial
> value. Then the synthesis will get rid of the register.

No, the initial value is set upon configuration, independently of the 
user's reset signal. There are only two ways to set this initial value:
1) "initial" block in Verilog or assignment at signal declaration in VHDL
2) with a parameter when you instantiate the register primitive