Re: [myhdl-list] Driving constants

[Jan L. <jan...@et...>]

Am 05.09.2011 um 00:40 schrieb Sébastien Bourdeauducq:

> On 09/04/2011 11:59 PM, Jan Langer wrote:
>> So my idea was to put the clock edge into the sensitivity list and  
>> you
>> get a clocked process that drives a constant,
>
> Ah, ok. :)
>
>> which in your case will get optimized away and behave as a normal  
>> constant.
>
> I'm afraid it won't. By default, FPGA registers are initialized at 0
> immediately after configuration. So if I want to drive a constant 1, I
> will get instead a register that will drive 0 until the first clock
> cycle, after which it drives 1.


Maybe you got a reset signal and can use that to set the initial  
value. Then the synthesis will get rid of the register.

-- 
Jan Langer
Professorship Circuit and System Design
Chemnitz University of Technology, Reichenhainer Str. 70, 09126 Chemnitz
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