Re: [myhdl-list] Convertible records

[Sébastien B. <seb...@mi...>]

On 09/02/2011 08:15 PM, Jan Langer wrote:
> maybe it would be a good idea to let the converter "ask" the class how
> it wants to be converted

Can't you infer the list of signals to convert from which ones get 
actually used?

What would be good imo (but with my limited knowledge of Python, I don't 
know if it's possible) is to simply name signal objects in the generated 
HDL according to how they were created. For example:

class some_class()
	def __init__(x):
		self.some_signal = x
(...)
b = Signal(bool(0))
some_object = some_class(b)
toVerilog(some_object.method)
  => gives a signal named "b"

class some_class()
	def __init__():
		self.some_signal = Signal(bool(0))
(...)
some_object = some_class()
toVerilog(some_object.method)
  => gives a signal named "some_object_some_signal"

(We should adopt a better naming scheme to guarantee the absence of 
collisions, but you get the idea)

This way (I believe) we could happily play with Python objects and still 
make nicely convertible/synthesizable code.

For ports, we can maybe give references to signal objects we want 
exported to the conversion functions.

Any comments?