Re: [myhdl-list] Convertible records

[Christopher F. <chr...@gm...>]

On 9/2/2011 8:53 AM, Sébastien Bourdeauducq wrote:
> On 09/02/2011 03:45 PM, Christopher Felton wrote:
>> A class/object that contains signals will not be converted.
>
> How difficult do you think it would be to get that to work?
>
> An alternative for me is the conversion of signal lists as parameters to
> the top functions, but this is not supported either.
>
> Which of the two is easier to implement?

Correct, neither of these are supported.  I don't know how much effort 
it would require to support these feature.  But I wouldn't mind 
researching this feature, because I recently also had a need to use a 
record type to convert some VHDL to MyHDL.

My basic thought would be to create a type in MyHDL, SignalStruct, and 
then create long unique variable names in the converted HDL.

Example:

    class MyBus(SignalStruct):
        def __init__(self):
            self.addr = Signal(intbv(0)[16:])
            self.data = Signal(intbv(0)[8:])
            # ...

    # ... some code
    bus = MyBus()
    # ... some generator
       bus.addr.next = x
       bus.data.next = y

The the converter, when in encountered a SignalStruct in the port list 
(parameter) or generator it would simple expand the name.
    // example of converted code
    bus_addr_mybus_t = x
    bus_data_mybus_t = y


The generated code would be a little obfuscated but I think the 
generated code should attempt to use the basics of the underlying HDL. 
This way, the Verilog can be Verilog and not SV.  The base class 
SignalStruct is used to guide the converters and built it can contain 
helper functions.

I am not familiar enough with the backend conversion to determine how 
much work it would be to find the primitive Signal type from a composite 
type in the converters.  But it seems like a nice enhancement and I 
would be willing to take it on.  But I have a couple other things I am 
trying to complete currently, it would need to be added to the queue.

Regards,
Chris Felton