Re: [myhdl-list] Convertible records

[Christopher F. <chr...@gm...>]

On 9/2/2011 7:16 AM, Sébastien Bourdeauducq wrote:
> Hi,
>
> The topic of records has been brought in quite some time ago:
> http://sourceforge.net/mailarchive/forum.php?thread_name=20040216193128.11905.qmail%40web60309.mail.yahoo.com&forum_name=myhdl-list
>
> However, while I managed to get them to work in simulation, they won't
> convert to VHDL or Verilog. I'm not an expert at Python, so I'm
> wondering if there is some fundamental issue that prevents this (useful)
> feature from being implemented, or is it that no one ever got down to
> it? Or am I just doing it wrong?
>

Conversion of a composite type is not supported.  The converted will 
examine the types to be converted and expects, either int or long, 
Signal, homogeneous list of signals, or a tuple of ints.

A class/object that contains signals will not be converted.  But the 
simulator has no problem modeling this convention.

Hope this helps,
Chris