[myhdl-list] Convertible records

[Sébastien B. <seb...@mi...>]

Hi,

The topic of records has been brought in quite some time ago:
http://sourceforge.net/mailarchive/forum.php?thread_name=20040216193128.11905.qmail%40web60309.mail.yahoo.com&forum_name=myhdl-list

However, while I managed to get them to work in simulation, they won't 
convert to VHDL or Verilog. I'm not an expert at Python, so I'm 
wondering if there is some fundamental issue that prevents this (useful) 
feature from being implemented, or is it that no one ever got down to 
it? Or am I just doing it wrong?

My example code is below.

Best regards,
Sébastien

from myhdl import *

class Binary:
	def __init__(self):
		self.a = Signal(intbv()[32:])
		self.b = Signal(intbv()[32:])

def Adder(clock, r, operands):
	@always(clock.posedge)
	def logic():
		r.next = operands.a + operands.b
	return logic

def TB(clock, r, operands):
	d = delay(10)
	@always(d)
	def tb():
		operands.a.next = operands.a + 1
		operands.b.next = operands.b + 1
		clock.next = not clock
		print r
	return tb

ops = Binary()
r = Signal(intbv()[32:])
clock = Signal(bool(0))

dut = Adder(clock, r, ops)
tb = TB(clock, r, ops)

# this is fine
sim = Simulation(dut, tb)
sim.run(50)

# this last line won't work
# myhdl.ConversionError: in file essai.py, line 11:
#    Unsupported attribute: a
toVHDL(Adder, clock, r, ops)