Re: [myhdl-list] Verilog flat file

[Christopher F. <chr...@gm...>]

On 8/11/11 8:58 AM, Wesley New wrote:
> Good Day,
>
> I am have been experimenting with including MyHDL in our toolflow setup
> that we are currently using and have noticed that the generated verilog
> is a flat file.
>
> I do understand that the idea behind MyHDL is that the designer is
> ultimely independent of any HDL language. But it is quite useful for me
> to know fpga resource usage per module/core in a design as this helps us
> when optimizing designs.
>
> So my question is, is there any way that I can keep the python hierarchy
> though into the generated verilog code?
>
> Thanks for you time.
>
> Regards
>
> Wesley
>

The idea was not to generate a flat file but rather have an 
"elaboration" phase in the Python code.  If you look at a MyHDL module 
there are two distinct sections of code.  The Python code inside a 
generator and the Python code outside of a generator.

Essentially, the code outside of the generator can be any valid Python 
code.  The code inside the generator has to be conversion compatible. 
To support this "elaboration" phase and leverage the built in Python 
compiler the _hierarchy_ is lost.  The flat-file generation was a result 
of this.

The previous comments are to the best of my understanding.  Jan D. the 
creator and main (99.999%) developer can correct me if I am wrong.

Regards,
Chris Felton