[myhdl-list] Verilog flat file

[Wesley N. <we...@sk...>]

Good Day,

I am have been experimenting with including MyHDL in our toolflow setup that
we are currently using and have noticed that the generated verilog is a flat
file.

I do understand that the idea behind MyHDL is that the designer is ultimely
independent of any HDL language. But it is quite useful for me to know fpga
resource usage per module/core in a design as this helps us when optimizing
designs.

So my question is, is there any way that I can keep the python hierarchy
though into the generated verilog code?

Thanks for you time.

Regards

Wesley