Re: [myhdl-list] Wait within @always()

[Uri N. <ur...@gm...>]

On 3 August 2011 17:03, Christopher Felton <chr...@gm...> wrote:

> On 8/3/2011 2:50 AM, Uri Nix wrote:
>
>> Hi,
>>
>> I'm using MyHDL to model a FSM, and would like to wait/delay the state
>> transitions, something like this:
>>
>> @always(clk.posedge)
>>  def logic():
>>     if state == t_State.ONE:
>>         state.next = t_State.TWO
>>         # wait for something comparable to myhdl.delay(x)
>>     ...
>>
>> If I understand correctly, this would require changing the function's
>> sensitivity list dynamically - is it possible?
>> I'd prefer to keep using the @always() pattern instead of yielding
>> explicitly.
>>
>> Cheers,
>> Uri
>>
>>
> Using the @instance approach isn't too overbearing (not too many yields).
>
>   @instance
>   def logic():
>      while True:
>         yield clk.posedge
>
>
>         if state == t_State.ONE:
>            state.next = t_State.TWO
>            yield delay(133)
>         # ... rest of the state-machine conditions
>
>   return logic
>
> The only yields you require are the initial clk and where ever you want the
> delays.  I would think something like the above should work for modeling.
>
> Note : this will not be convertible (might convert but not synthesizable).
>  If you want it to be convertible & synthesizable (C&S) you can add a
> variable (using the above method) and have a simple counter of clock ticks
> for the delay.  Or use @always(clk.posedge) and a Signal for a counter of
> clock events.
>
>
> Attached is the example I tested.
>
> Regards,
> Chris Felton
>
>
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>
Thanks, works like a charm!
As this is comparable to SystemC's SC_THREAD/wait() idiom, it also helped me
understand the yield business better.