Re: [myhdl-list] A Reviewers Thoughts ...

[Angel E. <ang...@gm...>]

On Fri, Jul 8, 2011 at 6:54 AM, Christopher Felton
<chr...@gm...> wrote:
> I have stumbled upon this presentation a couple times;
>
> http://seti.berkeley.edu/sites/default/files/gordon_casper_myhdl_presentation.pdf.
>
> The last slide is interesting, it is the brief summary of the author's
> concluding strengths and weaknesses of MyHDL.
>
> Strengths
> -----------
>  * The power of Python
>    * Supporting Libraries
>    * Flexibility
>
>  * Fast accurate functional simulations
>
> Weaknesses
> ------------
>  * Flat Conversion
>
>  * Limited Datatypes
>
>  * Manual Process
>
>
> I am surprised to see the "Flat Conversion" protested frequently.  I
> have not found this to be a weakness of any kind.  Have others found
> this to be a weakness?

Well, I am definitely not a power user of MyHDL, but I recently
attended a training course for Xilinx tools and one thing that we
learned is that it is possible to tell the synthesizer to "keep the
hierarchy" for a given (or all) module(s). Apparently this can lead to
more predictable synthesis. Also this makes sure that the module
interface signals are not lost during the synthesis/traslate/map
process, which makes it easier to add probes (e.g. a ChipScope) that
peek on those signals.

Angel