Re: [myhdl-list] Signal has multiple drivers - Solution ?

[Christopher F. <chr...@gm...>]

On 6/16/2011 7:46 AM, Sadique Sheik wrote:
> Hi Benoit,
>
> Thanks for the quick reply. It was very informative.
>
> I still have a few quick queries though.
>>
>> The easiest sample of such an arbiter is a multiplexer:
>>
>> def mux2(addr1, addr2, sel, addr):
>>    @always_comb:
>>    def muxLogic():
>>      addr.next = addr1
>>      if sel == 1:
>>        addr.next = addr2
>>    return muxLogic
>
> The multiplexer doesn't seem to solve the problem, atleast the way i see
> it. It seems that now instead of using the 'addr' signal i will endup
> driving the 'sel' signal by multiple components/locations.
>

The multiplexer solves the specific problem of multiple drivers.  It 
might not solve the *design* issue.  Per the description thus far, you 
only have one communication channel to the RAM.  You need to decide how 
this resource (RAM addr and data) are shared.  What are the "rules" for 
sharing.

As Benoit suggested, you might need some sort of arbitration (you can 
look at the wishbone documentations, or other on-chip buses for some 
examples).  A Dual-Port RAM might be appropriate in your case, if you 
have a separate writer and reader.

In general, once you determine the rules for sharing, the implementation 
can be a mux, a bunch of ORs (or ANDs).  As you read, tri-states are 
usually avoided for on-chip bus sharing.

Chris