Re: [myhdl-list] Signal has multiple drivers - Solution ?

[Sadique S. <sa...@in...>]

Hi Benoit,

Thanks for the quick reply. It was very informative.

I still have a few quick queries though.
> 
> The easiest sample of such an arbiter is a multiplexer:
> 
> def mux2(addr1, addr2, sel, addr):
>   @always_comb:
>   def muxLogic():
>     addr.next = addr1
>     if sel == 1:
>       addr.next = addr2
>   return muxLogic

The multiplexer doesn't seem to solve the problem, atleast the way i see
it. It seems that now instead of using the 'addr' signal i will endup
driving the 'sel' signal by multiple components/locations.

In the case of only two components, its alright because you can use one
of the components as a master and the other as a slave that relies on
the other component to set the correct select signal.

Did i get that right ? Or did i miss something very crucial .. 


> In the case of your RAM, a common seen practice is to have two `raddr`
> (read address) input in you module and two associated `dout` (data
> output) allowing two simultaneous read to happen from different
> modules.
This sounds good to me. I am going to go ahead and use it for my
simulations.

Although, I wonder how things are gona work if there are multiple (more
than 2) components, wont that just increase the number of ports ?

May be i should do some proper literature reading and get my basics
right..