[myhdl-list] Signal has multiple drivers - Solution ?

[Sadique S. <sa...@in...>]

Hi, 

I am absolutely new to HDL (just started 3 weeks ago!). 

I started with some reading on VHDL but fell in love with MyHDL.
I have been trying to do some basic simulations where i use a simple
RAM. I basically copied it from the documentation. 
http://www.myhdl.org/doc/0.6/manual/conversion_examples.html#ram-inference

Now in my simulation i use the addr signal in more than one location to
read from the ram. While simulating, everything works as expected. But
when i try conversion to VHDL it complains :

Signal has multiple drivers: addr

A bit of googling on this issue tells me that I should either set the
signal to "tristate" while i am not using it or use a "resolution
function."

A quick search in MyHDL documentation tells me that tristate thing is
not a very nice thing to do. Can some one tell me how this is usually
handled ? 

Can I get an example on how to define and use a "resolution function".

Thanks a lot
Sadique