Re: [myhdl-list] It should be possible to use a @process decorator wherever you can use @always

[Angel E. <ang...@gm...>]

On Sun, Jun 5, 2011 at 11:36 AM, Jan Decaluwe <ja...@ja...> wrote:
> On 06/02/2011 09:27 AM, Günter Dannoritzer wrote:
>> On 02.06.2011 08:55, Angel Ezquerra wrote:
>> ...
>>>
>>> I am all for simple software an libraries, but I would say that this
>>> addition would hardly make MyHDL more complex. Everything could stay
>>> the same. After all it would just be a matter of doing:
>>>
>>> process = always
>>> process_comb = always_comb
>> ...
>>
>>> From the stand point of implementation it is simple, but how about from
>> the standpoint of users?
>>
>> Think about a new user who is not familiar with any HDL and you explain
>> her she can use either always or process to achieve that?
>>
>> How would that compare to learning a new programming language and the
>> manual tells you that you can create i.e. classes with the keyword
>> 'class' or if you wish also with the keyword 'klasse'.
>>
>> In my opinion that would be very confusing for me if I learn a language new.
>
> I fully agree with that.
>
> There may sometimes be a good reason to change a name in
> favor of another one. However, I believe there should always be one
> clearly preferred one, and one clearly deprecated one that
> will be phased out over time.
>
> Defining equivalent aliases is a no-go. It is bound to create much
> more confusion than it would solve. I don't know of an example of a
> software language that does so, for good reasons.

Jan,

I understand your reasoning and I don't really disagree with it. Going
through your previous email I also understand why you chose the word
"always" rather than "process". However I find that a bit unfortunate
for two reasons:

- The MyHDL syntax has (in my humble and very inexperienced opinion)
more of a VHDL look than a Verilog look. I think that you have
strengthened that opinion with your recent blog posts in which you
criticized the way that Verilog "signals" work, compared to VHDL. It
is thus a bit unexpected that the basic building block of MyHDL is
named after a Verilog construct rather than a VHDL one.

- I personally find the word "always" quite disconnected from its
intended purpose (both in Verilog and in MyHDL), while I find the word
"process" much closer to what a MyHDL generator represents.

That being said, given that my (very limited) background is VHDL, it
is entirely possible that had I worked with Verilog rather than with
VHDL I would have the opposite opinion and that I would find the use
of "always" natural and fitting :-)

Angel