Re: [myhdl-list] It should be possible to use a @process decorator wherever you can use @always
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From: Jan D. <ja...@ja...> - 2011-06-05 09:26:06
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On 06/01/2011 10:41 PM, Angel Ezquerra wrote: > It would be nice if myhdl defined @process as an alias for @always. > While it is a very minor thing, using @always feels somewhat alien > when you come to myhdl from VHDL. In addition I feel that the word > "process" is more descriptive than "always" in this context, and > matches better its use in MyHDL. Also, because always and always_comb > match the corresponding Verilog keywords, it gives the impression that > MyHDL is Verilog centric while I don't think that is the case. Thus > providing a way to make your code look more VHDL like would be nice. Let me explain why I chose 'always' and not 'process'. One of my goals with MyHDL is to stimulate the use of the synchronous design template, which I believe is underused in traditional HDL design. A major obstacle in Verilog is that it doesn't make a difference between signals and variables, like VHDL. For this reason, MyHDL follows the VHDL example here. Therefore, MyHDL is based on VHDL at the core. However, in Verilog it is much easier to express that something is sensitive to an *edge* instead of signal change. You can do that right in the sensivity list. In VHDL, the edge sensitivtiy is hidden somewhere in the code. For the synchronous design template, this means that half of the time, the process is triggered for no reason. For this reason, I chose Verilog's model for sensitivity. Reusing 'always' therefore seemed the logical choice. Moreover, the syntactic similarity between the following two forms: @always(clock.posedge, reset.negedge) always @(posedge clock, posedge reset ) just seemed like a nice coincidence. However, note that it was never was the intention to make MyHDL "look" like Verilog or VHDL. MyHDL is implemented as pure Python and tries to look like Python. On the other hand, when some good concept can be re-used from earlier HDLs, there is no reason to invent another name for it. The bottom line is that 'always' and 'process' seem similar, but are really quite different in the way sensitivity is expressed. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com |