Re: [myhdl-list] Using MyHDL with existing infrastructure

[Christopher F. <chr...@gm...>]

On 6/2/2011 8:01 AM, Christopher Felton wrote:
> <snip>
>>
>> One important aspect I'd like to preserve is the ability to place a top
>> level port intended to be connected to the PowerPC deep within the
>> hierarchy of the design without having to bring the signals all the
>> way to the top level explicitly. I haven't seen a way to do this in
>> MyHDL, but it seems like it should be possible since the resulting
>> VHDL ends up with a flattened hierarchy anyway.
>>
<snip>
>       toVHDL(BurriedInstance, clk, rst, data_in, data_out)
>
(d'oh, hit send to early)

You will need the latest MyHDL release (0.7).  The only issue might be 
running MyHDL simulations.  You might want to use the __debug__ and 
define some simple logic to enable MyHDL simulations.

Below is a snippet of the VHDL generated:

architecture MyHDL of BurriedInstance is
begin
     P1:ppc port map(clk, rst, data_in, data_out);

end architecture MyHDL;

Regards,
Chris Felton