[myhdl-list] Using MyHDL with existing infrastructure
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jandecaluwe
From: glenn <jon...@ca...> - 2011-06-01 22:45:20
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Hello, Currently I use Simulink with Xilinx System Generator to generate DSP designs in VHDL which I then use in a board with well defined peripherals and an FPGA-PowerPC interface for setting/reading registers on the FPGA. To do this, I have scripts that automatically generate a PCORE from the XSG design by generating the necessary bbd and mpd files. The bbd file is trivial to generate. To generate the mpd, which contains information about the top level ports of the design, the tools are able to figure out the top level ports of the Simulink design. Special blocks are used to represent signals that should be connected to the PowerPC bus. These blocks wrap the "gateway in/out" blocks that are used to instantiate a top level port. I've taken a brief look at the code used by the toVHDL function, and it seems like it should be possible to do something similar. One way might be to define a subclass of Signal that when encountered by the analyzer provides information for the mpd file, but otherwise acts just like a normal signal. One important aspect I'd like to preserve is the ability to place a top level port intended to be connected to the PowerPC deep within the hierarchy of the design without having to bring the signals all the way to the top level explicitly. I haven't seen a way to do this in MyHDL, but it seems like it should be possible since the resulting VHDL ends up with a flattened hierarchy anyway. I appreciate any suggestions. I'm happy to clarify anything that might be confusing. Thanks in advance, Glenn |