Re: [myhdl-list] intbv wrap

[Jan D. <ja...@ja...>]

On 05/11/2011 04:01 PM, Christopher Felton wrote:
>
> On 5/11/2011 7:31 AM, Ben wrote:
>> Hi Chris,
>>
>> I am following your struggle with this feature with great interest, as
>> I do think this would be an interesting addition to MyHDL, however, as
>> an hypothetical future extension to MyHDL, I think this would deserve
>> a MEP ... For now, If I want to understand your design decisions, I
>> have to dig into my mails and look for the relevant part. I for one
>> have for instance a question about the restrictions you enforce. See
>> below.
> Here is the original MEP I wrote.  It is not complete and has not been
> updated based on the conversations had here.  Also, this MEP simply
> exists in my user space right now.
>
> http://www.myhdl.org/doku.php/user:cfelton:projects:wrap
>
> I will try and update the MEP based on the latest developments when time
> permits.  More comment below.
>>
>> On Tue, May 10, 2011 at 13:27, Christopher Felton
>> <chr...@gm...>   wrote:
>>> I made a couple of minor adjustments to this patch.
>>>
>>>    1. Made the wrap function private (_wrap) and moved _wrap to __wrap.  The
>>> wrap function should not be used directly because it will not covert
>>> correctly.  I think for a future (todo) enhancement the wrap function can be
>>> made public and handled by the converter.  This is an involved modification.
>>>    For now I think it is good to advertise the wrap function was private.
>>
>> I don't really understand the reason of such an enforcement on min and
>> max for the wrapping. Let's be for a moment the devil's advocate and
>> say I want my intbv to be between -3 and 12. Why would MyHDL prevent
>> me to have it wrapped ?
>
> The reason is, we want to model natural behavior of a n-bit word.  An
> n-bit word automatically wraps, by truncating the most-significant bits,
> when assigned.  We want to prevent the automatic wrap in the example
> because additional logic is required.  This is the same for the
> saturate.  This enhancement is simply trying to add the natural
> occurring wrap of a n-bit binary word.  To model this behavior correctly
> the min and max need to be the full range of the binary word.

What is "natural" depends entirely on your perspective. If your
perspective is representation, I agree. But if your perspective is
modeling in terms of modulo arithmetic, the restrictions would be
incomprehensible.

I really think MyHDL should make a difference with Verilog/VHDL here.
We should concentrate on modeling first, and only then on
conversion/synthesizability. As the intbv example shows, sometimes
there isn't even a price to pay! Moreover, we can always impose
additional restrictions for convertiblity, but we may also find
ways to implement more powerful solutions than with Verilog/VHDL.

>
> This is a little confusing because the intbv lets you assign arbitrary
> min and max for design checking (which is a good thing).  But note, this
> checking (bound checking) is only enforced during the design, MyHDL
> simulations.
>
> To do the wrapping in your example, the logic would explicitly need to
> be added to the design.  IMO is good and why I think the wrap() will be
> public in the future once direct use of the function is convertible.
>
> This enhancement is intended to handle the generic wrap case.  That
> should not be part of the intbv object.  But rather model the inherent
> wrapping of a bit-vector.
>
>>
>>>
>>>    2. Added myrange to a slot, _range.
>>
>> This is a coding style decision. This _range is used at only one
>> place, and completely redundant with the existence of _nrbits. I don't
>> think it deserves a slot.
>>
>>>
>>>    3. Modified a couple comments.
>>>
>>
>> BTW, did you got the testsuite to run ? To run the "core" one, I don't
>> think you would need py.py. It uses unittest, which is included in
>> your python distribution.
>
> Yes, your additions are perfect and IMO correct.  I reran the tests in
> the core test suite and they are part of the patch.  Thanks again for
> doing this work!
>
>>
>> Best Regards
>> Benoît
>>
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>
>
>
> ------------------------------------------------------------------------------
> Achieve unprecedented app performance and reliability
> What every C/C++ and Fortran developer should know.
> Learn how Intel has extended the reach of its next-generation tools
> to help boost performance applications - inlcuding clusters.
> http://p.sf.net/sfu/intel-dev2devmay


-- 
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