Re: [myhdl-list] MyHDL / ModelSim cosim
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From: Jan D. <ja...@ja...> - 2011-05-06 19:37:53
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On 05/05/2011 02:48 PM, Christopher Felton wrote: > There was an old thread (last post 31 May 2005, same subject line) that > addressed a memory leak in Modelsim which also occurred in cver and > Icarus. I don't know if this was resolved but the issue still exists in > the current releases with Modelsim. > > In a cosimulations that I was running a simulation would exceed 10GB of > resident memory usage. And the simulation would crawl along when this > occurred. > > The fix was to release the handles created by vpi_scan, example > > ~~~~~~~~~~~ Code Snip ~~~~~~~~~~~~~~~~~~ > // ~line 416 of myhdl_vpi.c > while ((value_s.value.str = strtok(NULL, " ")) != NULL) { > reg_handle = vpi_scan(reg_iter); > vpi_put_value(reg_handle,&value_s, NULL, vpiNoDelay); > vpi_free_object(reg_handle); // **<-- Added line > } > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > This had to be added in four spots (~line 125, 198, 301, 416). The > reg_handle and net_handle in the reg and net iterator loops had to be > released for each object retrieved (at least for modelsim). After this > change my memory usage top out at 222MB (no more leak). > > I did not create a patch because I didn't have time to regression test > cver and Icarus. > > I can provide a patch if desired. Should a separate directory and > myhdl_vpi.c and Makefile be created for mti in the Cosimulation directory? Yes, that's the right way, and thanks for debugging this. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com |