Re: [myhdl-list] Modules interface information

[Oscar D. <osc...@gm...>]

2011/5/5 Günter Dannoritzer <dan...@we...>:
> Am 05.05.2011 15:45, schrieb Oscar Diaz:
>
> ...
>
> BTW, I did not follow in that example what I was telling you earlier
> about inferring the bit width from the input signal.

Suppose that I want to implement the adder in a structural way with
1-bit adders:

def add1bit(a, b, carry_in, x, carry_out):
    ...

def adder(a, b, x):
    assert len(a) = len(b)
    carry = [Signal(0) for i in range(len(a))]
    add_1bit_list = [ add1bit( a(i), b(i), carry(i), x(i), carry(i+1)
) for i in range(len(a)) ]
    ...

I don't need an explicit width parameter to know how many instances of
add1bit is needed, and I enforce the restriction of 'a' and 'b' to
have the same width.

Again, I think I should pick another better example :P

>
> Cheers, Guenter
>
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Oscar Díaz
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