Re: [myhdl-list] Modules interface information

[Christopher F. <chr...@gm...>]

<snip>
 > The internal logic will determine it by the
> specified interface signal. - Though works only for input signals. When
> I tried this the last time for output signals, the convertor got
> confused, because I was using information from the output signal and it
> thought I tried to use it as an input.
>

This is only true if the information accessed was used inside of a 
generator?  If the bit-width (len) and such is accessed outside of the 
generators it should not be a problem.

Do you have a simple example?  Something like this?

def  ioid(a,b,x):

    @always_comb
    def rtl_something():
        x.next = a[int(len(x)/2)] ^ b[int(len(x)/4)]

Chris