Re: [myhdl-list] Modules interface information

[Günter D. <dan...@we...>]

Am 05.05.2011 12:00, schrieb Oscar Diaz:
...
> In traditional HDL you have a well-defined interface in the modules:
> i.e. VHDL has entity declarations with generics and ports, each with a
> well-defined type. So, you can easily create an IP core and someone
> can easily see the entity description and hopefully use it correctly.

I agree that you need some documentation about what is an input, output,
or parameter. But there is some advantage to not specify the port too
specific. You can create the code in a generic way and specify by the
interfacing signals its behavior. No need to specify whether the input
is 8 bit or 16 bit wide. The internal logic will determine it by the
specified interface signal. - Though works only for input signals. When
I tried this the last time for output signals, the convertor got
confused, because I was using information from the output signal and it
thought I tried to use it as an input.

One interesting idea is conditional instantiation as shown in the manual
based on a parameter:

http://www.myhdl.org/doc/current/manual/modeling.html#conditional-instantiation

I haven't tested that, but assume you could do it based on the signal
type as well. So if the interface signal is of type intbv, use some
implementation that is e.g. different from the implementation than the
implementation when the input signal is a bool type. ... or any other
type you can imagine.

Cheers, Guenter