Re: [myhdl-list] MyHDL project debriefing

[Jan D. <ja...@ja...>]

On 04/27/2011 05:25 AM, Tom Dillon wrote:
> Some comments:
>
>
> On 04/26/2011 03:13 PM, Jan Decaluwe wrote:
>> I just finished a MyHDL project that was lot of fun,
>> and I thought some of you might be interested in a few highlights.
>> You will understand that I cannot go in too much detail.
>>
>> The starting point for this image processing algorithm
>> was a spec in words. The deliverable was RTL VHDL code
>> and a regression test suite.
>>
>> To have a verification reference, the customer agreed
>> that I developed a high-level untimed model of the
>> algorithm in pure Python. This have been a great help,
>> and the customer actually agreed to sign of on it.
>
> I too have found Python great for this.
>
>> I developed all functional modules in MyHDL. There were
>> a number of arithmetic modules (multipliers, dividers) and
>> algorithmic modules (e.g. sorting). In some cases, pipelining
>> was needed (to meet timing), in others iterative
>> implementations (to save area.) A unit-based test-driven
>> development approach worked great in such cases.
>>
>> All MyHDL modules were individually converted to VHDL. The
>> convertor's ability to add all the resizing/conversion
>> details proved again a great help. (I also discovered
>> some bugs in the process.
>> The modules were stitched together in VHDL using Sigasi HDT,
>> a VHDL IDE from Sigasi, a company that I am coaching
>> (as a consultant, director and shareholder.) Sigasi HDT was
>> also used to develop the test bench code. Recommended for
>> anyone who (also) uses VHDL :-)
>>
> Was there a reason not to covert at a higher level and get rid of the
> need for Sigasi HDT?

As per customer requirements, the final deliverable was VHDL RTL
code for synthesis, and a VHDL-based regression suite.
The customer has to be able to use the deliverable directly in his
VHDL-only design flow.

The test bench involves file IO, input and output, in a
way not supported by conversion. So for the top-level
test bench I used a direct VHDL approach, including
VHDL configurations to set up different scenario's.

For the top-level, I could have used conversion, however I
wanted to keep some hierarchy (for clarity for the customer),
and as you know this takes some work. As I didn't use  the
MyHDL top-level itself, there was little value in this,
especially because Sigasi HDT makes stitching things
together structurally very easy

>
>> The high-level Python model generated input data as well
>> as expected output. A single (configurable) VHDL test bench
>> takes the input and dumps the output. The regression
>> test suite simply runs all test scenarios and diffs
>> actual and expected output.
>
> Was a MyHDL test bench too slow to run the top level test? Or why use VHDL?

See above - VHDL handoff was a customer requirement.

MyHDL would have been slower, but that would not have been a major issue.

In the ideal world, I would of course prefer to use a MyHDL only
design flow and only use VHDL/Verilog as a backend format. But in
this first engagement with this customer I'm happy that I have
been able to show the value of Python as a first step.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com