Re: [myhdl-list] MyHDL project debriefing

[Tom D. <td...@di...>]

Some comments:


On 04/26/2011 03:13 PM, Jan Decaluwe wrote:
> I just finished a MyHDL project that was lot of fun,
> and I thought some of you might be interested in a few highlights.
> You will understand that I cannot go in too much detail.
>
> The starting point for this image processing algorithm
> was a spec in words. The deliverable was RTL VHDL code
> and a regression test suite.
>
> To have a verification reference, the customer agreed
> that I developed a high-level untimed model of the
> algorithm in pure Python. This have been a great help,
> and the customer actually agreed to sign of on it.

I too have found Python great for this.

> I developed all functional modules in MyHDL. There were
> a number of arithmetic modules (multipliers, dividers) and
> algorithmic modules (e.g. sorting). In some cases, pipelining
> was needed (to meet timing), in others iterative
> implementations (to save area.) A unit-based test-driven
> development approach worked great in such cases.
>
> All MyHDL modules were individually converted to VHDL. The
> convertor's ability to add all the resizing/conversion
> details proved again a great help. (I also discovered
> some bugs in the process.
> The modules were stitched together in VHDL using Sigasi HDT,
> a VHDL IDE from Sigasi, a company that I am coaching
> (as a consultant, director and shareholder.) Sigasi HDT was
> also used to develop the test bench code. Recommended for
> anyone who (also) uses VHDL :-)
>
Was there a reason not to covert at a higher level and get rid of the 
need for Sigasi HDT?

> The high-level Python model generated input data as well
> as expected output. A single (configurable) VHDL test bench
> takes the input and dumps the output. The regression
> test suite simply runs all test scenarios and diffs
> actual and expected output.

Was a MyHDL test bench too slow to run the top level test? Or why use VHDL?