[myhdl-list] MyHDL project debriefing

[Jan D. <ja...@ja...>]

I just finished a MyHDL project that was lot of fun,
and I thought some of you might be interested in a few highlights.
You will understand that I cannot go in too much detail.

The starting point for this image processing algorithm
was a spec in words. The deliverable was RTL VHDL code
and a regression test suite.

To have a verification reference, the customer agreed
that I developed a high-level untimed model of the
algorithm in pure Python. This have been a great help,
and the customer actually agreed to sign of on it.

I developed all functional modules in MyHDL. There were
a number of arithmetic modules (multipliers, dividers) and
algorithmic modules (e.g. sorting). In some cases, pipelining
was needed (to meet timing), in others iterative
implementations (to save area.) A unit-based test-driven
development approach worked great in such cases.

All MyHDL modules were individually converted to VHDL. The
convertor's ability to add all the resizing/conversion
details proved again a great help. (I also discovered
some bugs in the process.)

The modules were stitched together in VHDL using Sigasi HDT,
a VHDL IDE from Sigasi, a company that I am coaching
(as a consultant, director and shareholder.) Sigasi HDT was
also used to develop the test bench code. Recommended for
anyone who (also) uses VHDL :-)

The high-level Python model generated input data as well
as expected output. A single (configurable) VHDL test bench
takes the input and dumps the output. The regression
test suite simply runs all test scenarios and diffs
actual and expected output.

Timing was not trival to meet. However, using this methodology
it was possible to run trial synthesis early on and get
feedback from trial place&route, so that meaningful
optimizations (in some case large) to the RTL could be
made, integrated in the RTL development flow.

A pity it's over :-)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com