Re: [myhdl-list] Testbench problems

[Christopher F. <chr...@gm...>]

On 4/19/2011 1:09 PM, Terry Brown wrote:
> I am in the process of writing a module implementing registers in an fpga.  I
> have the module logic working.
>
> In the testbench, I instantiate the module and generate a clock and use this to
> handle reset:
>
>
>      @instance
>      def reset_stim():
>          yield delay(1)
>          reset_n.next = 0
>          dstb.next = 0
>          rdstb.next = 0
>          din.next = 0
>          adr.next = 0
>          i2c_stop.next = 0
>          status_input.next = 0
>          yield delay(100)
>          reset_n.next = 1
>
> Then I use another @instance for the actual test. The test simply toggles the
> inputs to the module to write and read the registers.
>
> To generate the read and write cycles, I use a combination of delays and
> assignments.  However, in verilog, I am used to using tasks to define these
> operations, then calling them.
>
> I want to use the high-level capability of python to code the test, but I
> haven't been able to make it work with defined tasks of the verilog type that
> use delays to manipulate signals.

Make your "tasks" generators and then use yield test_readit()

Below is an example from a USB interface model that I have used.

#---------------------------------------------------------------------------
# In main testbench
yield fx2Model.WriteAddress(0x0101, 1)


     def WriteAddress(self, addr, data):

         wbuf = [0xDE, 0xCA, 0x01, 0x00, 0x00, 0x01, 0xFB, 0xAD, 0x00]
         rbuf = [0]*9

         wbuf[3]  = (addr >> 8) & 0xFF
         wbuf[4]  = addr & 0xFF
         wbuf[5]  = 1
         wbuf[8]  = data

         self.Write(wbuf, self.EP2)
         while not self.IsEmpty(self.EP2):
             yield delay(2*self.IFCLK_TICK)
         while not self.IsData(self.EP6, 9):
             yield delay(2*self.IFCLK_TICK)

         for i in range(9):
             rbuf[i] = self.Read(self.EP6)

         for i in range(9):
             assert wbuf[i] == rbuf[i]
#---------------------------------------------------------------------------

The above WriteAddress is a generator because it contains the yield. 
The top-level testbench can yield to the generator, you can yield as 
many levels down as you need.

Hope that helps.
Chris Felton