[myhdl-list] Testbench problems

[Terry B. <tt...@gm...>]

I am in the process of writing a module implementing registers in an fpga.  I 
have the module logic working.

In the testbench, I instantiate the module and generate a clock and use this to 
handle reset:


    @instance
    def reset_stim():
        yield delay(1)
        reset_n.next = 0
        dstb.next = 0
        rdstb.next = 0
        din.next = 0
        adr.next = 0
        i2c_stop.next = 0
        status_input.next = 0
        yield delay(100)
        reset_n.next = 1

Then I use another @instance for the actual test. The test simply toggles the 
inputs to the module to write and read the registers.

To generate the read and write cycles, I use a combination of delays and 
assignments.  However, in verilog, I am used to using tasks to define these 
operations, then calling them.  

I want to use the high-level capability of python to code the test, but I 
haven't been able to make it work with defined tasks of the verilog type that 
use delays to manipulate signals.  

For example, I would like to do this:

def readit (adr):
  yield clk.posedge
  yield delay(1)
  reg_module_address.next = adr
  yield clk.posedge
  yield delay(1)
  return reg_module_data_out

And then in the test do this:
def testit():
  for reg in reglist:
    rddata = readit(reg)
    print str(rddata)

But when I do that the readit function doesn't apparently do anything--no 
clocking occurs, no delays occur.  I get no runtime errors, but the function 
doesn't execute.  If I place the readit code inline within the testit function, 
it all works properly.

What am I missing?  Must be something basic.  If it's not and someone wants to 
see the actual code, let me know.

Thanks for the help.

Terry Brown