Re: [myhdl-list] CASE versus IF (MyHDL)

[Jan D. <ja...@ja...>]

On 04/15/2011 08:49 AM, Jan Coombs wrote:
> On 12/04/11 10:49, David Rodríguez wrote:
>> Dear MyHDL distribution list,
>>
>> I am going through the MyHDL traning material. I have almost completed the
>> RTL combinatorial and sequential modelling section.  I need to find some
>> time to type some code and see how good my understanding  of everything is.
>> However, there is something that bothers me. I have found in the VHDL that
>> there is a big difference when CASE statements and IF statements are used.
>>
>> I tend to use CASE when I want a given MUX to be inferred (e.g. MUX 4-to-1).
>
> I'm translating a small processor design from Verilog to MyHLD, so
> this point interests me, as there are large and irregular muxes
> implied in the design.
>
> Although I am interested to see that the Verilog/VHDL translation
> is as simple as possible, perhaps with good synthesis tools there
> will be very little difference in final logic compiled?

Jan:

A "true" case, specifying disjoint conditions, can make a
difference. In such cases, the convertor should be able
to map MyHDL if-then structures to a VHDL/Verilog case.



>
> Hopefully I will have some practical answers in a few days.
>
> Jan Coombs
>
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Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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