Re: [myhdl-list] CASE versus IF (MyHDL)

[Jan C. <jan...@mu...>]

On 12/04/11 10:49, David Rodríguez wrote:
> Dear MyHDL distribution list,
>
> I am going through the MyHDL traning material. I have almost completed the
> RTL combinatorial and sequential modelling section.  I need to find some
> time to type some code and see how good my understanding  of everything is.
> However, there is something that bothers me. I have found in the VHDL that
> there is a big difference when CASE statements and IF statements are used.
>
> I tend to use CASE when I want a given MUX to be inferred (e.g. MUX 4-to-1).

I'm translating a small processor design from Verilog to MyHLD, so 
this point interests me, as there are large and irregular muxes 
implied in the design.

Although I am interested to see that the Verilog/VHDL translation 
is as simple as possible, perhaps with good synthesis tools there 
will be very little difference in final logic compiled?

Hopefully I will have some practical answers in a few days.

Jan Coombs