Re: [myhdl-list] New MyHDL Tutorial Available.

[Christopher F. <chr...@gm...>]

On 4/13/2011 7:09 AM, Jan Decaluwe wrote:
> On 04/13/2011 05:00 AM, Christopher Felton wrote:
>
>>
>> The code can be retrieved from :
>> hg clone https://bitbucket.org/dsptronics/myhdl_tutorials
>
> Ok, great, I got access and made some text edits.
> (The code still runs :-))
>
> There is a remark I forgot previously: why no reset signals?
> I guess fpga software does the "right" thing
> at initialization, but as a matter of policy,
> isn't adding a reset a good idea?
>

Yes and no, I was not trying to exploit the fact that the FPGA has a POR 
and the state of the FF is known at power on (config release).  But 
rather, when possible not to use resets.  At least I have been 
encouraged in the past.  In this case, the >= handles the "unknown" 
cases.  If the counter comes up either the >= will get the value back in 
range or the first LED cycle will be short.  Both acceptable behavior.

If most feel more comfortable with a reset I am not against it.

Note, not using resets only makes sense in a small subset of circuits. 
When I was in CO. there were a lineage of folks that worked on fibre 
controller chip-sets.  This was their policy, never to use resets (crazy 
huh).  This flowed over to other companies and work in the area, 
including the SigProc-FPGA work I was doing at the time.  And best of my 
knowledge they have shipping chip-sets with limited use of resets (not 
FPGA).  As mentioned, for most I don't think this is practical, you have 
to be very careful that you understand all the possible init states and 
know that each is handled correctly.

Chris Felton