Re: [myhdl-list] New MyHDL Tutorial Available.

[David R. <dav...@gm...>]

Yes it does. As I said, I was being "picky".

Regarding the reset signal. Do you have a power_up pin on that FPGA that
shows you when power has been enable? The reset signal could be hooked up to
that pin.

Do we have to explain how to pin assignment in the document?

Chris, are you using a Mac for this...I have a couple of questions that
would be a good idea to ask off the MyHDL list for Mac user...obviously
regarding MyHDL.



On Wed, Apr 13, 2011 at 1:21 PM, Christopher Felton
<chr...@gm...>wrote:

> On 4/13/2011 2:55 AM, David Rodríguez wrote:
> > Hi,
> >
> > I'm being "picky" but it will be a good idea to change variable CLK_RATE
> > to CLK_48Mhz. It makes more sense when reading the code as the LED rate
> > of change is also named LED_RATE. In doing so, it is easier to
> > understand things like Nloops=CLK_48Mhz*LED_RATE.
> >
>
> Does CLK_FREQ work for you?  I don't want to explicitly state 48MHz
> because we are targeting multiple boards, all which have different
> frequencies.
>
> Chris Felton
>
> (I also noticed I can't do math in comments :), I will fix if someone
> already hasn't )
>
> <snip>
>
>
>
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-- 
David Rodríguez Martin
Cambridge,UK