[myhdl-list] CASE versus IF (MyHDL)

[David R. <dav...@gm...>]

Dear MyHDL distribution list,

I am going through the MyHDL traning material. I have almost completed the
RTL combinatorial and sequential modelling section.  I need to find some
time to type some code and see how good my understanding  of everything is.
However, there is something that bothers me. I have found in the VHDL that
there is a big difference when CASE statements and IF statements are used.

I tend to use CASE when I want a given MUX to be inferred (e.g. MUX 4-to-1).

IF will be used if you want to a sequence of events to happens (synthesis
tools would infer a "daisy-chain" of MUXs).

It is important to say that what I've observed probably is an outcome of
something I am doing wrong or some lack of experience. But I would like to
know what the opinion about the no CASE statement in Python is and if that
can limit MyHDL capability to model digital systems.

 regards,

-- 
David Rodríguez Martin
Cambridge,UK