Re: [myhdl-list] Floating Point Libraries

[Christopher F. <chr...@gm...>]

On 4/11/2011 3:35 PM, Christopher Lozinski wrote:
> Christopher Felton and I have been having a discussion about libraries.
> I am moving it to the mailing list, because I think many people would be
> interested.
>
> We have been talking about how to represent floating point in MyHDL, and
> how to work with it in Verilog.  Basically the plan is to implement a
> multiply in MyHDL as a python * operator.   Then export it by calling
> some library.  The question is which library.

Note, this approach will take some work and it will be a module on-top 
of MyHDL.  It will be faster to first implement the fp libraries in 
MyHDL or decide how to interface with external fp libs.

>
> So Wayne  Radohonski is quite committed to supporting his Altera board.
>
> The libraries he wants to use are the Altera libraries.  Phase lock
> loop, and then floating point multiply.
> His point is that building phase lock loops is even more important than
> the floating point multiplier.

Do you mean, to instantiate the PLLs that are in the Altera FPGA or to 
design an ADLL (all digital lock loop)?

Do you know which Altera fp libraries are targeted?  They might cost $$ 
and not many people might have access to them.

>
> Both because supporting an Altera board is important, and because of the
> policy of one engineer at a time, I want to support the boards Wayne
> wants in this endeavor.  So the plan is to create two MyHDL classes, one
> for a floating point signal, and one for a floating point multiplier.
> When exporting it will generate the right Verilog code to call the
> Altera libraries.  Later it will call other libraries.  One at a time.
>
> How does that sound?
>

This is a similar approach Andrew L, just need to be careful which mixed 
approach to take.  The DE2 boards are mid-size Cyclone FPGAs, he 
probably has the 70k DE2 board?

Chris Felton