[myhdl-list] Floating Point Libraries

[Christopher L. <loz...@fr...>]

Christopher Felton and I have been having a discussion about libraries.  
I am moving it to the mailing list, because I think many people would be 
interested.

We have been talking about how to represent floating point in MyHDL, and 
how to work with it in Verilog.  Basically the plan is to implement a 
multiply in MyHDL as a python * operator.   Then export it by calling 
some library.  The question is which library.

So Wayne  Radohonski is quite committed to supporting his Altera board.

The libraries he wants to use are the Altera libraries.  Phase lock 
loop, and then floating point multiply.
His point is that building phase lock loops is even more important than 
the floating point multiplier.

Both because supporting an Altera board is important, and because of the 
policy of one engineer at a time, I want to support the boards Wayne 
wants in this endeavor.  So the plan is to create two MyHDL classes, one 
for a floating point signal, and one for a floating point multiplier.  
When exporting it will generate the right Verilog code to call the 
Altera libraries.  Later it will call other libraries.  One at a time.

How does that sound?

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org