Re: [myhdl-list] help - hot bit encoder

[Jan C. <jan...@mu...>]

On 08/04/11 08:31, Jan Coombs wrote:
> On 03/04/11 12:02, Jan Decaluwe wrote:
>  > Jan:
>  >
>  > You struggle . . .
>
> Yes.  . . .

I now have simulation working correctly, though I'm not sure if 
this is the simplest way to write the code I want.

Conversion to VHDL or Verilog is a problem.  I get the error:

Traceback (most recent call last):
   File "./encodeHotBit_map11.py", line 83, in <module>
     test_ehb()
   File "./encodeHotBit_map11.py", line 81, in test_ehb
     toVHDL(hotBit2binary, iv, ov, Width)
   File 
"/usr/local/lib/python2.6/dist-packages/myhdl/conversion/_toVHDL.py", 
line 145, in __call__
     genlist = _analyzeGens(arglist, h.absnames)
   File 
"/usr/local/lib/python2.6/dist-packages/myhdl/conversion/_analyze.py", 
line 165, in _analyzeGens
     _isMem(obj) or _isTupleOfInts(obj)
AssertionError


Any suggestions?  Jan Coombs