Re: [myhdl-list] FW: Floating-point support --> Fixed-point

[Karl K. <kk...@be...>]

I am interested in the status of Fix point support in MyHDL. Is there some
effort on the way to implement this. I am a newbie on the Python side but
may be able to contribute from the hardware side. I have done some work on
an ASIC fix point DSP component library in Verilog in the past.

Cheers,
Karl Kaiser

On Thu, Mar 3, 2011 at 6:34 AM, Christopher Felton
<chr...@gm...>wrote:

> <snip>
>> On a related sidenote, the situation is completely different for
>> fixed point. I have little experience with it, but great interest
>> in enhancing MyHDL support for this. It seems this could be a
>> "killing feature", as Verilog doesn't have it and I think the VHDL
>> approach can be improved. I have been following Chris Felton's
>> work with great interest. As it happens, I am now doing a project
>> involving fixed point and after that I hope to have time
>> to work on it in MyHDL.
>>
>
> I do agree, Fixed-point will always be a popular topic in HDLs (ASIC/FPGA).
>  Tom Dillon has done some work in this area in the past as well.  Both VHDL
> and SystemC have been working on standardizing fixed-point notation (
> http://www.vhdl.org/fphdl/,
> http://standards.ieee.org/getieee/1666/download/1666-2005.pdf).  They are
> both good starts for what is currently supported.  But I believe with
> MyHDL/Python you will have much more power than the VHDL/SystemC approaches.
>
> One mistake I made with my approach was using the "Q" notation.  We had a
> sub-thread on this in comp.dsp (
> http://www.dsprelated.com/showmessage/133353/2.php), which notation makes
> sense for fixed-point.  The "Q" (sometimes "S", etc) has some limitation.
>  The notation used in the SystemC LRM (or VHDL?) is a better notation
> because you can move the "point" outside of the actual word size.  I have
> wanted to update my write-up and examples with a better notation and
> examples of the "point" outside the word size.  I will keep you posted.
>
> As for the floating-point, I think most inquires, on this topic, have to do
> with more than simple floating-point support.  I believe they would like a
> panacea; take a sequential algorithm, in double precision, and convert it to
> hardware.  As mentioned and I agree with Jan D., this is a large task, and a
> task that is not in the boundaries of the MyHDL scope.  Someone with
> experience in this area (doctoral topic?) could build support on top of
> MyHDL (Algorithm translator --> MyHDL --> RTL) or something.
>
> .chris
>
>
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-- 
Best regards,

Karl Kaiser | 408 306 1755