[myhdl-list] My take on MyHDL weaknesses - and solutions

[Jan D. <ja...@ja...>]

Hereby my take on current weaknesses, and possible
solutions. In preparation of marketing actions!

If useful we can of course move this type of info
to the website also.

Performance
-----------
Compared to compiled VHDL and Verilog simulators, MyHDL is
slow as a dog. MyHDL's implementation tries to limit the
overhead, but performance will always be limited by the
underlying Python interpreter.

Solution 1: Education. Raw performance doesn't necessarily
translate directly into designer's performance, especially
in the initial exploratory phases of a project. Otherwise
no one would be using Python, Perl, php or tcl.

Solution 2: The PyPy project (future). Python doesn't have
to be slow: by employing clever JIT techniques, performance
can be improved drastically e.g. 5-10x. I believe that MyHDL
is a good candidate for this type of optimization. The day
this happens would be one of the most important ones in
MyHDL's history: the performance limitations would for a
large part go away, and it would be the ultimate validation
of the concept: benefitting from advances without having to
do anything yourself :-)

Perception
----------
MyHDL is sometimes perceived as a "one man show". Moreover,
I'm long enough in this business to understand that no new
EDA technology has a chance of truly succeeding without a
strong backing from Silicon Valley. For the record: I have
no plans of moving, it's too much fun living in a
non-country :-)

Solution: exactly the kind of initiatives that are being
taken right now.

Audience mismatch
-----------------
MyHDL is strongly in the "digital hardware design is a
special kind of software development" camp. However, the
vast majority of hardware designers doesn't see things this
way. Schematic entry may be dead in practice, but not yet in
the minds.

Solution: Patience. It's a waste of time to argue with
people who only use irrational arguments, which is how I
would characterize the arguing skills of many hardware
designers - they just don't *really* understand HDL-based
design and synthesis. We have to keep our ideas alive until
the new generation takes over. Moreover, there is another
reason for hope: software designers who realize that FPGAs
can be seen as "just" another computing platform. (Warning:
we will then face the opposite problem of people wondering
why things have to be done at such a "low level". It's
lonely in the middle :-))

Lack of killer features
-----------------------
The benefits of MyHDL are real but they remain somewhat
abstract, e.g. "managing complexity".

Solution: a strong value proposition would be concrete
features that many hardware designers want but that are not
offered by their current tools. I have two things in mind
currently: a good fixed-point class with transparent support
by the convertor, and SystemVerilog-style interfaces in
MyHDL that could be converted to VHDL and Verilog, that don't
have something similar.

Lack of star IP
---------------
Open source star IP could make MyHDL very attractive. I am
referring to projects such as Leon SPARC in VHDL. Ideally,
someone would implement some hot new technology as an IP
core in MyHDL. The problem is that such a project may need
more effort than the MyHDL project itself.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com