Re: [myhdl-list] help - hot bit encoder

[Jan D. <ja...@ja...>]

Jan:

You struggle with the difference between elaboration
and simulation. All code outside generators is elaborated
once by the Python interpreter. All code inside generators
is alive during simulation.

In particular, logical operators on Signals during
elaboration don't magically create something that
tracks value changes throughout simulation.

Also, a structural view is not always the best
choice (although elaborated code can be as complex
as required without jeopardizing convertibility.)
Perhaps you should consider all this shadow signal
business as "advanced usage" and first understand
what you can do with good old RTL style code.

For example, the following code passes your tests,
converts, and is synthesisable. (Expressing the
don't care conditions which are probably there
is not possible in this way however.)

def encodeHotBit(iv, ov, Width=4):

     @always_comb
     def logic():
         ov.next = 0 # avoid state
         for i in range(len(iv)):
             if iv[i] == 1:
                 ov.next = i

     return logic
   

Jan


On 04/03/2011 12:04 PM, Jan Coombs wrote:
> #!/usr/bin/env python
>
> ''' progress
>    #04 asked for help
>    #03 generates VHDL, cleaner, but problem unchanged
>    #02 compiles, but each o bit is iv(15)!!!
>    #01 tried using lists - oops
> '''
> from myhdl import *
>
>
> def encodeHotBit(iv, ov, Width=4):
>    olt = [Signal(bool(False)) for i in range(Width)]
>    for j in range(Width):
>      for i in range(2**Width):
>        if (i%(2**(j+1)))>= (2**j):
>          olt[j] = olt[j] or iv(i)
>    oc = ConcatSignal(*reversed(olt))
>    @always_comb
>    def assign():
>      ov.next = oc
>    return assign
>
>
> Width=4
> iv = Signal(intbv(0)[Width**2:])
> ov = Signal(intbv(0)[Width:])
>
> toVerilog(encodeHotBit, iv, ov, Width)
> toVHDL(encodeHotBit, iv, ov, Width)
>
> # set up a test bench
> #from random import randrange
> def tb():
>    dut = encodeHotBit(iv, ov, Width)
>    @instance
>    def check():
>      yield delay(10)
>      for i in range(16):
>        iv.next = 2**i
>        yield delay(10)
>        print i, iv, ov
>        #assert 2**ov == iv
>    return dut, check
>
> # the entry point for the py.test unit test framework
> def test_ehb():
>      sim = Simulation(tb())
>      sim.run()
>
> test_ehb()
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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