Re: [myhdl-list] rosettacode submission

[Jan C. <jan...@mu...>]

On 02/04/11 14:45, Christopher Felton wrote:
> I was curious if something was submitted to rosettacode?  Jan D. version
> could be submitted.

I wrote to Mauro Panigada, who set this challenge, asking for 
guidance as to what to post. Although I was not surprised that he 
wanted my school-homework style solution, I intended to clean it up 
first. Perhaps I should just post both.

Jan Coombs
-- 

Mauro Panigada wrote:
I think it is very interesting, I will take a deeper look in my 
spare time!
Quickly viewing the attached sources, it seems to me your solution 
meets
task requirements; post your own solution on RC, if you've not done so
already, this is my only advice:)

About giving MyHDL its own category, I disagree: after all, it is 
Python
exploiting Python's capabilities, packages and so on. So I believe 
it is
enough to use the libheader "tag" (or similar, but if I remember 
well RC
still does not distinguish among libraries in the "C meaning" and
libraries/packages/modules/whatever in "other language meaning"). 
However,
comments page on RC are also to discuss this kind of topic, and 
there are a
lot of persons there that likely would disagree with me.

Thanks you for having brought to my attention MyHDL! It's that sort 
of thing
I like a lot (though currently I've drifted mainly to musical 
composition in
my spare time, just to break with programming a bit --- but 
hardware design
is still in my mind :D)

Have a good day (here in Italy it's 7:30 AM)


On Mon, Mar 21, 2011 at 11:48 PM, Jan <jan...@mu...> 
wrote:

 > > hi Mauro,
 > >
 > > I have tackled this problem using MyHDL (myhdl.org), a python 
library
 > > which is designed for hardware simulation.
 > >
 > > Attached is my very structured solution, also the solution of 
the author of
 > > MyHDL.  I'm not sure which approach meets your illustrative 
goal better, and
 > > would like advice.
 > >
 > > MyHDL meets a number of your mentioned future goals, being able to
 > > represent clocks and latches, and is also capable of exporting 
VHDL or
 > > Verilog for real hardware design.
 > >
 > > Because of the capabilities of MyHDL, I think that it should 
have a
 > > separate language category in RC, rather than being combined 
with python,
 > > what do you think?
 > >
 > > Kind regards,  Jan Coombs.
 > >
 > >