Re: [myhdl-list] rosettacode submission

[Jan D. <ja...@ja...>]

I couldn't resist to post my take on this. I realize
that the whole handling of lists is sometimes confusing,
however I think that is especially so for small
examples like this with a "forced" structural
approach.

I have added comments to clarify what I'm doing.
I would use the opportunity to illustrate conversion
to Verilog and VHDL, and unit testing. This is
all in my example code.

I have used the SystemVerilog code as an example -
the unit test worked first time right.


On 03/21/2011 12:32 PM, Jan Decaluwe wrote:
> I believe the most important thing is to look good :-)
>
> I don't think we should be holier than the pope - ADA and
> SystemVerilog in this case. Both use basic bit-operations
> to model basic gates - even an xor as opposed to what
> the spec says. We should be allowed to do the same and
> start from the Half-Adder.
>
> I would keep things simple and first do the whole thing
> using lists of signals. Then, I would use a top-level wrapper
> that would only do the conversion from intbv's to lists and vice
> versa. Note that, in a real design environment, this is only
> strictly necessary if you want to convert the adder as
> a top-level - something not very likely.
>
> The ConcatSignal in your code really creates a signal and should
> be used outside generators, if conversion is an issue
> (and probably otherwise also, to use Signals in the "intended" way.)
> The functional equivalent that returns a value is myhdl.concat.
>
> I would *definitely* include a simple test bench, using `assert`
> that could be used by a framework such as py.test.
>
> Jan
>
> On 03/19/2011 01:07 PM, Jan Coombs wrote:
>> While helping with some code debugging for another rosettacode page, I noticed that there is a simple hardware category:
>>
>> http://rosettacode.org/wiki/Four_bit_adder
>>
>> I now have some questions about my potential submission:
>>
>> 1) Could posting this on rosettacode generate an unwelcome influx of MyHDL newbies?
>>
>> 2) My 'ConcatSignal(*reversed' phrase did not work. Have I missed something, or do I have to use an @always_comb and loop?
>>
>> 3) Does my code have about the right level of commenting for a novice reader? Should I expand signal names for easier reading?
>>
>> Any further suggestions for making this submission attractive, understandable, and a good representation of MyHDL would be much appreciated.
>>
>> Jan Coombs
>>
>>
>>
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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