Re: [myhdl-list] rosettacode submission

[Felton C. <chr...@gm...>]

On Mar 19, 2011, at 7:07 AM, Jan Coombs wrote:

> While helping with some code debugging for another rosettacode page,  
> I noticed that there is a simple hardware category:
>
>  .0200
>
> I now have some questions about my potential submission:
>
> 1) Could posting this on rosettacode generate an unwelcome influx of  
> MyHDL newbies?
I would not be concerned about this.

>
> 2) My 'ConcatSignal(*reversed' phrase did not work.  Have I missed  
> something, or do I have to use an @always_comb and loop?
I am not familiar with *reversed?  Will need to look at this when I  
have some time.

>
> 3) Does my code have about the right level of commenting for a  
> novice reader?  Should I expand signal names for easier reading?
I think it is fine but I would use the port names defined on the  
rossetta page.  That makes it easier to follow for someone working  
through the page.

>
> Any further suggestions for making this submission attractive,  
> understandable, and a good representation of MyHDL would be much  
> appreciated.
>
> Jan Coombs

Couple additional comments,

I would add self-checking capabilities to the testbench vs. simply  
printing out the results.

Also, I know this example follows the page description for a  
"simulation" on the rosetta code page (your code has the comment  
"synthesis"?).  Instead of a bottom up approach I think it would be  
nice to show an actual "behavioral" synthesis and show that the tools  
generate the full-adder as described.  In my opinion, other than an  
academic exercise, creating a the 4-bit adder built from HA and FAs  
has limited use.  I do realize that is probably not the intent of the  
example for the page.

Some of the other examples don't create functions/modules for the  
primitive operations.  It makes the example very explicit but with  
that it is verbose.

Chris Felton