Re: [myhdl-list] FW: Floating-point support

[Jan C. <jan...@mu...>]

On 22/02/11 21:43, Christopher Felton wrote:
    . . .
> MyHDL is an RTL similar to VHDL and Verilog.  It has the same level support.
>   It does not do higher level synthesis.

Yes, thanks, but it seems much more friendly than the VHDL 
synthesis and simulation tools I've used for prototyping to date.

> Because MyHDL is exists in the Python eco you get a tone of power with your
> RTL but not high-level synthesis.  This could be a separate project that
> works with MyHDL but it is a considerable effort (see other high-level
> synthesis research).

Starting to learn Python itself has been a major leap forward for 
me, only having previous experience of logic design and low level 
languages. Features new to me, and particularly useful to this 
project are unbounded ints and lists.

The parts of David Bluebaugh's request that interested me are the 
provision of synthesizable modules to perform basic FP 
calculations, and pipeline components to connect them. (I'm 
probably taking a little liberty with his words here)

Some sort of front end to automatically string these modules 
together based on a higher level description is probably beyond my 
interest and capability. I'm struggling to get up to speed with 
MyHDL. The low level components interest me as they are needed for 
another project.

Jan Coombs