Re: [myhdl-list] Converting std_logic_vector to signed and vice versa

[Jan D. <ja...@ja...>]

Thomas Heller wrote:
> I have written a small module in MyHDL which takes
> incoming waveforms x and y, multiplies them with an
> amplitude value and adds an offset tho them.
> 
> The VHDL code that MyHDL generates uses signed(15 downto 0)
> for the values:
> 
> entity DSP is
>      port (
>          clock: in std_logic;
>          x: in signed (15 downto 0);
>          y: in signed (15 downto 0);
>          amplitude: in signed (15 downto 0);
>          offset: in signed (15 downto 0);
>          xout: out signed (15 downto 0);
>          yout: out signed (15 downto 0)
>      );
> end entity DSP;
> 
> Now, my top level module uses std_logic_vector(15 downto 0)
> for these signals.  How can I use the generated module?

signed, unsigned, and std_logic_vector are in VHDL terminology
"closely related". This implies that you can directly convert
them to each other using the target type name as a casting function.

For minimal overhead, the type conversions can be done right
in the instantiation. They work at both sides of a named
association, i.e. for both formal and actual.

Jan

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