[myhdl-list] Converting std_logic_vector to signed and vice versa

[Thomas H. <th...@ct...>]

I have written a small module in MyHDL which takes
incoming waveforms x and y, multiplies them with an
amplitude value and adds an offset tho them.

The VHDL code that MyHDL generates uses signed(15 downto 0)
for the values:

entity DSP is
     port (
         clock: in std_logic;
         x: in signed (15 downto 0);
         y: in signed (15 downto 0);
         amplitude: in signed (15 downto 0);
         offset: in signed (15 downto 0);
         xout: out signed (15 downto 0);
         yout: out signed (15 downto 0)
     );
end entity DSP;

Now, my top level module uses std_logic_vector(15 downto 0)
for these signals.  How can I use the generated module?

Thanks,
Thomas